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this document is a general product descript ion and is subject to change without notice. hynix does not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev 1.2 / dec. 2009 1 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 1 gb nand flash H27U1G8F2B
rev 1.2 / dec. 2009 2 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash document title 1 gbit (128 m x 8 bi t) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. may. 13. 2008 preliminary 0.1 1) correct table 5. mode selection. jul. 4. 2008 preliminary 0.2 1) correct read id 4th cycle value. (table 15, figure 19) aug. 19. 2008 preliminary 1.0 1) delete preliminary mar. 13. 2009 1.1 1) insert fbga package sep. 28. 2009 1.2 1) correct fbga pkg ball configuration dec. 03. 2009 cle ale ce we re wp mode l l l h h x during read (busy)
rev 1.2 / dec. 2009 3 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 bus width. - address / data multiplexing - pinout compatiblity for all densities supply voltage - 3.3 v device : vcc = 2.7 v ~3.6 v memory cell array - (2 k + 64) bytes x 64 pages x 1024 blocks page size - (2 k + 64 spare) bytes block size - (128 k + 4 k spare) bytes page read / program - random access : 25 us (max.) - sequential access : 25 ns (min.) - page program time : 200 us (typ.) fast block erase - block erase time: 2 ms (typ) electronic signature - 1st cycle : manufacturer code - 2nd cycle : device code - 3rd cycle : internal chip number, cell type, number of simultaneously programmed pages. - 4th cycle : page size, block size, organization, spare size copy back program - fast data copy without external buffering cache read - internal buffer to improve the read throughput chip enable don't care - simple interface with microcontroller status register - normal status register (read/program/erase) hardware data protection - program/erase locked during power transitions. data retention - 100,000 program/erase cycles (with 1 bit / 528 byte ecc) - 10 years data retention package - H27U1G8F2Btr-bx : 48-pin tsop1 (12 x 20 x 1.2 mm) - H27U1G8F2Btr-bx (lead & halogen free) - H27U1G8F2Bfr-bx : 63-ball fbga (9 x 11 x 1.0 mm) - H27U1G8F2Bfr-bx (lead & halogen free)
rev 1.2 / dec. 2009 4 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 1. summary description hynix nand H27U1G8F2B series have 128 m x 8 bit with spar e 4 m x 8 bit capacity. the device is offered in 3.3 v vcc power supply, and with x8 i/o interface. its nand cell provides the most cost-eff ective solution for the solid state mass storage market. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. the device contains 1024 blocks, composed by 64 pages. a program operation allows to write the 2112 byte page in typical 200 us and an erase operation can be performed in typical 2.0 ms on a 128 k byte block. data in the page can be read out at 25ns cycle time per by te. the i/o pins serve as the ports for address and data input/ output as well as command input. this interface allows a re duced pin count and easy migration towards different densities, without any rearrang ement of footprint. commands, data and addresses are sy nchronously introduced using ce, we , re , ale and cle input pin. the on-chip program/erase controller automates all program and erase func tions including pulse repetition, where required, and inter- nal verification and margining of data. the mo dify operations can be locked using the wp input. the chip supports ce don't care function. this function allows the direct download of the code from the nand flash memory device by a microcontroller, since the ce transitions do not stop the read operation. the output pin r/b (open drain buffer) signals the status of the device during each operation. in a system with multiple memories the r/b pins can be connected all together to provide a global status signal. even the write-intensive systems can take advantage of th e H27U1G8F2B series extended reliability of 100 k program/ erase cycles by providing ecc (error correcting code) with real time mapping-out algorithm. the copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. data read out after copy back read is allowed. this device includes also extra features li ke otp/unique id area, read id2 extension. the H27U1G8F2B is available in 48-tsop1 12 x 20 mm and 63-fbga 9 x 11 mm. 1.1 product list part number organization vcc range package H27U1G8F2B x8 2.7v ~ 3.6v 48-tsop1 / 63-fbga
rev 1.2 / dec. 2009 5 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash vcc vss wp cle ale re we ce io0~io7 r/b nc nc nc nc nc nc nc nc cle ale vss vss vss vcc vcc nc nc nc wp re ce we rb nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 nc nc nc nc nc nc nc pre nc nc nc nc nc nc nc a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 uhukgm???? gggggminh ggggggo?_p figure 2 : 48-tsop1 / 63-fbga contact, x8 device io7 - io0 data input / outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect r/b ready / busy vcc power supply vss ground nc no connection figure 1 : logic diagram table 1 : signal names 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [
rev 1.2 / dec. 2009 6 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 1.2 pin description table 2 : pin description note : 1. a 0.1uf capacitor should be connecte d between the vcc supply voltage pin an d the vss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. pin name description io0 ~ io7 data inputs/outputs the io pins allow to input command, address and da ta and to output data during read / program operations. the inputs are latched on th e rising edge of write enable (we ). the i/o buffer float to high-z when the device is deselected or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we ). ale address latch enable this input activates the latching of the io inputs inside the address register on the rising edge of write enable (we ). ce chip enable this input controls the selection of the device. we write enable this input acts as clock to latch command, addre ss and data. the io inputs are latched on the rise edge of we . re read enable the re input is the serial data-out co ntrol, and when active drives th e data onto the i/o bus. data is valid trea after the falling edge of re which also increments the inte rnal column address counter by one. wp write protect the wp pin, when low, provides an hardware protec tion against undesired modify (program / erase) operations. r/b ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection
rev 1.2 / dec. 2009 7 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 3 : array organization table 3 : address cycle map note: 1. l must be set to low. 2. 1st & 2nd cycle are column address. 3. 3rd to 4th cycle are row address. io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0a1a2a3a4a5a6a7 2nd cycle a8 a9 a10 a11 l (1) l (1) l (1) l (1) 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 plane 2 k bytes 64 bytes i/o0 ~ 7 1 page = (2 k + 64) bytes 1 block = (2 k + 64) bytes x 64 pages = (128 k + 4 k) bytes 1 device = (128 k + 4 k) bytes x 1024 block page buffer 1024 blocks per plane 1023 1024 1 0 . . .
rev 1.2 / dec. 2009 8 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 4 : command set note : with the ce don't care option ce high during latency time does not stop the read operation table 5 : mode selection function 1st 2nd 3rd 4th acceptable command during busy page read 00h 30h - - read for copy-back 00h 35h - - read id 90h - - - reset ffh - - - yes page program 80h 10h - - copy back pgm 85h 10h - - block erase 60h d0h - - read status register 70h - - - yes random data input 85h - - - random data output 05h e0h - - cache read start 31h - - cache read exit 3fh - - - cle ale ce we re wp mode hllrisinghx read mode command input l h l rising h x address input (4 cycles) hllrisinghh write mode command input l h l rising h h address input (4 cycles) lllrisinghh data input l l l h falling x data output x x x h h x during read (busy) xxxxxh during program (busy) xxxxxh during erase (busy) xxxxxl write protect xxhxx0 v / vcc stand by
rev 1.2 / dec. 2009 9 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 2. bus operation there are six standard bus operations that control the device. these are comma nd input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on ch ip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip en- able low, command latch enable high, address latch enable lo w and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modify oper ation (write/erase) the write protect pin must be high. see figure 5 and table 12 for detail s of the timings requirements. 2.2 address input. address input bus operation allows the in sertion of the memory address. to insert the 28 addresses needed to access the 1gbit 4 clock cycles are needed. addresses are accepted with chip enable low, addr ess latch enable high, command latch enable low and read enable high and latched on the ri sing edge of write enable. moreover for commands that starts a modify operation (write/erase) the writ e protect pin must be high. see figure 6 and table 12 for details of the timings requirements. 2.3 data input. data input bus operation allows to feed to the device the data to be programmed. the data insertion is serially and timed by the write enable cycles. data are accepted only with chip enable low, address latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 7 and table 12 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the memory arra y and to check the status register content, the lock status and the id data. data can be serial ly shifted out toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latch enable low. see figure 8, 9, 10 and tabl e 12 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protect pin is low. in this condition modify operation do not start and the content of the memory is not altered. write protect pin is not latched by write enable to ensure the protection even during the power up. 2.6 standby. in standby the device is deselected, output s are disabled and power consumption reduced.
rev 1.2 / dec. 2009 10 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 3. device operation 3.1 page read. upon initial device power up, the device defaults to read mo de. this operation is also initiated by writing 00h and 30h to the command register along with four address cycles. in two consecutiv e read operations, the second one does need 00h command, which four address cycles and 30h command initiates that operation. second read operation always re- quires setup command if first read operation was executed using also random data out command. two types of operations are available: random read , serial page read. the random read mode is enabled when the page address is changed. the 2112 bytes of data within the selected page are transferre d to the data registers in less than 25 us(tr). the system controller may detect the completion of this data transfer (tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 25 ns cycle time by sequentially pulsing re . the repetitive high to low transitions of the re clock make the device output the da ta starting from the selected column address up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data output command. the column address of next data, which is going to be ou t, may be changed to the address which follows random data output command. random data output can be operated multiple times regardless of how many times it is done in a page. after power up, device is in read mode so 00h command cycle is not necessary to start a read operation. any operation other than read or random data output causes device to exit read mode. check figure 11, figure 12, and figure 13 as references. 3.2 page program. the device is programmed basically by page, but it does al low multiple partial page programming of a word or consec- utive bytes up to 2112, in a single page program cycle. th e number of consecutive partial page programming operation within the same page without an interv ening erase operation must not exceed 8; for example, 4 times for main array (1time/512byte) and 4 times fo r spare array (1time/16byte). a page program cycle consists of a serial data loading period in which up to 2112 bytes of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is pr ogrammed into the appropriate cell. the serial data loading period begins by inputting the serial data input command (80h), followed by the four cycle ad- dress inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be ente red, may be changed to the address which follows random data input command (85h). rand om data input may be operated multiple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the progra mming process. writing 10h al one without previously en- tering the serial data will not initiate the programming process. the internal wr ite state controller automatically executes the algorithms and timings nece ssary for program and verify, th ereby freeing the system cont roller for other tasks. once the program process starts, the read status register command may be entered to read the status register. the system controller can detect the completion of a program cycle by monitoring the r/b output, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be chec ked. the internal write verify detects only errors for "1"s that are not successfully programmed to "0 "s. the command register remains in re ad status command mode until another valid command is written to the command register. figure 14 and figure 15 detail the sequence.
rev 1.2 / dec. 2009 11 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 3.3 block erase. the erase operation is done on a block basis. block address lo ading is accomplished in two cycles initiated by an erase setup command (60h). only address a18 to a27 is valid whil e a12 to a17 are ignored. the erase confirm command (d0h) following the block address loading initiate s the internal erasing process. this two- step sequence of setup followed by ex- ecution command ensures that memory contents are not accidentally er ased due to external noise conditions. at the rising edge of we after the erase confirm command input, the inte rnal write controller handles erase and erase- verify. once the erase process starts, the read status register comm and may be entered to read the status register. the system controller can detect the completion of an erase by monitoring the r/b output, or the status bit (i/o 6) of the status reg- ister. only the read status command and reset command are va lid while erasing is in progre ss. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure 18 details the sequence. 3.4 copy-back program. the copy-back program is configured to quickly and efficientl y rewrite data stored in one page without utilizing an ex- ternal memory. since the time-c onsuming cycles of serial a ccess and re-loading cycles are removed, the system perform- ance is improved. the benefit is especially obvious when a po rtion of a block is updated and the rest of the block is also needed to be copied to the newly assign ed free block. the operation for perfor ming a copy-back program is a sequential execution of page-read without serial a ccess and copying-program with the address of destination page. a read operation with "35h" command and the address of the source page move s the whole 2112byte data into the internal data buffer. as soon as the device returns to ready state, op tional data read-out is allowed by toggling re , or copy back command (85h) with the address cycles of destination page may be written. the program confirm command (10h) is required to actually begin the programming operation. data input cycle for modifyin g a portion or multiple distan t portions of the source page is allowed as shown in figure 17. "when there is a program-failure at copy-back operation, erro r is reported by pass/fail status. but, if copy-back opera- tions are accumulated over time, bit error due to charge loss is not checked by external e rror detection/correction scheme. for this reason, two bit error correction is re commended for the use of copy-back operation." figure 16 and figure 17 show the command sequence for the copy-back operation. please note that wp value is don't care during read for copy back, while it must be set to vcc when performing the program . 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or erase operation is comp leted successfully. after writ ing 70h command to the command register, a read cycle outputs the cont ent of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 13 for specific status register definitions, and figure 10 for spec ific timings requirements. the co mmand register remains in sta- tus read mode until further commands are issu ed to it. therefore, if the status regist er is read during a random read cycle, the read command (00h) should be given before starting read cycles. 3.6 read id. the device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad- dress input of 00h. four read cycles se quentially output the manufacturer code (adh), and the device code and 00h, 4th cycle id, respectively. the command register remains in read id mode until further commands are issued to it. figure 19 shows the operation sequence, while table 14 to table 17 explain the byte meaning.
rev 1.2 / dec. 2009 12 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operatio n will abort these operations. the contents of memory cells being altered are no longer valid, as th e data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value e0h when wp is high. refer to table 13 for device status after reset operation. if the device is already in re set state a new reset command will not be accepted by the com- mand register. the r/b pin transitions to low for trst after the reset command is written (see figure 20). 3.8 read cache the read cache function permits a page to be read from th e page register while another page is simultaneously read from the flash array. a read page command, as defined in 3. 1, shall be issued prior to th e initial sequential or random read cache command in a read cache sequence. the read cache function may be issued af ter the read function is complete (sr[ 6] is set to one). the host may enter the address of the next page to be read from the flash array. data output always begins at column address 00h. if the host does not enter an address to retrieve , the next sequential page is read. when the read cache function is issued, sr[6] is cleared to zero (busy). after the oper ation is begun sr[6] is set to one (ready ) and the host may begin to read the data from the previous read or read cache function. issuing an additional read cache function copies the data most recently read from the array into the page regist er. when no more pages are to be read , the final page is copied into the page register by issuing the 3fh command. the host may begin to read data from the page regi ster when sr[6]is set to one (ready). when the 31h and 3fh commands are issued, sr[6] sh all be cleared to zero (busy) until the page has finished being copied from the flash array. the host shall not issue a sequential read cache (31h) command after the last page of the device is read. figure 21 defines the read cache behavior and timings for the beginning of the cache operations subsequent to a read command being issued. sr[6] conveys whet her the next selected page can be read from the page register. figure 21 also shows the read cache behavior and timings for the end of cache operation.
rev 1.2 / dec. 2009 13 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 4. other features 4.1 data protection. the device is designed to offer protecti on from any involuntary program/erase during power-transitions. an internal volt- age detector disables all functions whenever vcc is below about 1.8 v (3.3 v version). wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down. a reco very time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figu re 22. the two-step command sequence for program/erase provides addi tional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the comple tion of a page program, erase, copy- back, cache program and random read completion. the r/b pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). it returns to high when the internal controll er has finished the operation. the pin is an open-drain driver thereby allowing two or more r/b outputs to be or-tied. because pull-up resistor value is related to tr(r/b ) and current drain during busy (i bu sy), an appropriate value can be ob tained with the following reference chart (figure 23). its value can be determined by the following guidance.
rev 1.2 / dec. 2009 14 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 6 : number of valid blocks note: 1. the 1st block is guaranteed to be a valid block at the time of shipment. table 7 : absulute maximum ratings note: 1. except for the rating "operating temperature range", stresses above those listed in the table "absolute maximum ratings" may cause permanent damage to the device. these ar e stress ratings only and operation of the device at these or any other conditions above those indica ted in the operating sections of this sp ecification is not implied. exposure to absolute maximum rating conditions for extended periods ma y affect device reliability. refer also to the hynix sure program and other relevant quality documents. 2. minimum voltage may undershoot to -2v during tr ansition and for less than 20ns during transitions. parameter symbol min typ max unit valid block number n vb 1004 1024 blocks symbol parameter value unit t a ambient operating temperature (temperature range option 1) 0 to 70 c ambient operating temperature (temperature range option 6) ? 40 to 85 c t bias temperature under bias ? 50 to 125 c t stg storage temperature ? 65 to 150 c v io (2) input or output voltage ? 0.6 to 4.6 v v cc supply voltage ? 0.6 to 4.6 v
rev 1.2 / dec. 2009 15 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 4 : block diagram address register/ counter program erase controller hv generation command interface logic command register data register io re buffers y decoder page buffer x d e c o d e r 1024 mbit + 32 mbit nand flash memory array wp ce we cle ale a27 ~ a0
rev 1.2 / dec. 2009 16 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 8 : dc and opea ting characteristics table 9 : ac test conditions parameter symbol test conditions 3.3 volt unit min typ max operating current sequential read i cc1 t rc = 25 ns, ce = v il, i out = 0 ma - 15 30 ma program i cc2 - - 15 30 ma erase i cc3 - - 15 30 ma stand-by current (ttl) i cc4 ce = v ih , wp = 0 v/v cc 1ma stand-by current (cmos) i cc5 ce = v cc -0.2, wp = 0/v cc 10 50 ua input leakage current i li v in = 0 to vc (max) - 10 ua output leakage current i lo v out = 0 to vcc(max) - 10 ua input high voltage v ih - 0.8 x v cc - v cc + 0.3 v input low voltage v il --0.3- 0.2 x v cc v output high voltage level v oh i oh = - 400 ua 2.4 - - v outpul low voltage level v ol i ol = 2.1 ma - - 0.4 v output low current (r/b ) i ol (r/b ) v ol = 0.4 v 8 10 - ma vcc supply voltage (erase and program) lockout v lko -1.8-v parameter value 3.3 volt input pulse levels 0 v to v cc input rise and fall times 5 ns input and output timing levels v cc / 2 output load (1.65v ? 1.95v & 2.5v - 3.6v) 1 ttl gate and cl = 50 pf
rev 1.2 / dec. 2009 17 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 10 : pin capacitance (ta = 25 ,
rev 1.2 / dec. 2009 18 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 12 : ac timing characteristics note : 1) if reset command (ffh) is written at ready st ate, the device goes into busy for maximum 5 us parameter symbol 3.3 volt unit min max cle setup time t cls 12 ns cle hold time t clh 5ns ce setup time t cs 20 ns ce hold time t ch 5ns we pulse width t wp 12 ns ale setup time t als 12 ns ale hold time t alh 5ns data setup time t ds 12 ns data hold time t dh 5ns write cycle time t wc 25 ns we high hold time t wh 10 ns address to data loading time t adl 70 ns data transfer from cell to register t r 25 us ale to re delay t ar 10 ns cle to re delay t clr 10 ns ready to re low t rr 20 ns re pulse width t rp 12 ns we high to busy t wb 100 ns read cycle time t rc 25 ns re access time t rea 20 ns re high to output hi-z t rhz 100 ns ce high to output hi-z t chz 30 ns ce high to ale or cle don?t care t csd 10 ns re high to output hold t rhoh 15 ns re low to output hold t rloh 5ns ce high to output hold t coh 15 ns re high hold time t reh 10 ns output hi-z to re low t ir 0ns re high to we low t rhw 100 ns we high to re low t whr 60 ns device resetting time (read/program/erase) t rst 5/10/500 1) us
rev 1.2 / dec. 2009 19 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 13 : status register coding table 14 : device identifier coding table 15 : read id data table io page program block erase read cache read coding 0 pass / fail pass / fail na na pass: ?0? fail: ?1? 1na na na na - 2na na na na - 3na na na na - 4na na na na - 5 ready/busy ready/busy ready/busy p/e/r controller bit active: ?0? idle:?1? 6 ready/busy ready/busy ready/busy ready/busy busy: ?0? ready:?1? 7 write protect write protect write protec t na protected: ?0? not protected: ?1? device identifier byte description 1 st manufacturer code 2 nd device identifier 3 rd internal chip number, cell type, etc. 4 th page size, block size, spare size, organization part number voltage bus width 1st cycle (manufacture code) 2nd cycle (device code) 3rd cycle 4th cycle H27U1G8F2B 3.3v x8 adh f1h 00h 1dh
rev 1.2 / dec. 2009 20 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash table 16 : 3rd byte of device identifier description table 17 : 4th byte of device identifier description description io7 io6 io5 io4 io3 io2 io1 io0 die / package 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not supported 0 1 write cache not supported 0 1 description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1kb 2kb 4kb 8kb 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time 45 ns 25 ns reserved reserved 0 0 1 1 0 1 0 1 block size (without spare area) 64k 128k 256k 512kb 0 0 0 1 1 0 1 1 organization x8 x16 0 1
rev 1.2 / dec. 2009 21 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 5 : command latch cycle figure 6 : address latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ tcls tcs twc tals tals tals tals talh talh talh talh twc twc twp twp twh twp twp twh twh tds col.add1 cle ce we ale i/ox col.add2 row add1 row add2 tds tds tds tdh tdh tdh tdh
rev 1.2 / dec. 2009 22 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 7 : input data latch cycle figure 8 : sequential out cycle after read (cle=l, we =h, ale=l) trc ce re i/ox r/b trea trr dout dout dout notes: transition is measured at +/-200mv from steady state voltage with load. this parameter is sampled and not 100% tested. (tchz, trhz) trhoh starts to be valid when frequency is lower than 33 mhz. trloh is valid when frequency is higher than 33 mhz. trea trhz trhz trea tchz tcoh trhoh treh twc tclh tch twp twh din 1 din 0 din final twh tdh tdh tdh tds tds tds twp twp cle ale ce i/ox we tals
rev 1.2 / dec. 2009 23 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 9 : sequential out cycle after read figure 10 : status read cycle w5& w53 w5(+ w5($ w&5 w5/2+ w55 w5($ w&+= w&2+ w5+= w5+2+ 'rxw 'rxw &( 5( ,2[ 5% 1rwhv7udqvlwlrqlvphdvxuhgdwp9iurpvwhdg\vwdwhyr owdjhzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw&+= w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhuwkdq 0+] w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &5 w '6 w 5($ w &+= w &2+ w 5+= w 5+2+ k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5(
rev 1.2 / dec. 2009 24 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 11 : read operation (read one page) figure 12 : read operation intercepted by ce cle ale ce i/ox we re r/d t wc t clr t rr 00h 30h col.add1 column address row address col.add2 row add1 row add2 busy dout n dout n+ dout m t wb t ar t r t rc t rhz g twb tar tchz tcoh trc tr trr busy 00h 30h dout n dout n+1 dout n+2 col. add1 col. add2 row add1 row add2 column address row address cle ce we ale re i/ox r/b
rev 1.2 / dec. 2009 25 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 13 : random data output cle ale ce re r/b i/ox we tclr 00h column address row address busy 30h 05h e0h dout n dout m dout n+1 dout m+1 col. add1 row add1 row add2 col. add2 column address col. add1 col. add2 tr trc twb tar trr twhr trea trhw
rev 1.2 / dec. 2009 26 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 14 : page program opeation cle ale ce re r/b i/ox we twc 80h col. add1 serial data input command column address notes : tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. row address read status command program command i/o0=0 successful program i/o0=1 error in program 1 up to m byte serial input col. add2 row add1 row add2 din n din m 10h 70h i/o twc twb tprog twhr twc tadl
rev 1.2 / dec. 2009 27 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 15 : random data in cle ale ce re r/b i/ox we twc 80h din n din m din j din k 85h 10h 70h i/o col. add1 col. add2 col. add1 col. add2 rwo add1 rwo add2 twc twb twhr tprog serial data input command random data input command column address column address row address notes : 1. tadl is the time from the we rising edge of final address cycle to the we rsing edge of first data cycle. serial input serial input program command read status command twc tadl tadl
rev 1.2 / dec. 2009 28 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 16 : copy back read with optional data readout cle ale ce re r/b i/ox we tclr 00h column address row address busy 35h 05h e0h dout n dout m dout n+1 dout m+1 col. add1 row add1 row add2 col. add2 column address col. add1 col. add2 tr trc twb tar trr twhr trea trhw
rev 1.2 / dec. 2009 29 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 17 : copy back program with random data input cle ce we twc twb tr trc tadl tprog twhr twb ale re 00h 35h 10h i/o 70h 85h data data data data 85h data data busy notes: 1. tadl is the time from the we rising edge of final address cycle to the we rising edge of first data cycle. column address column address data out data in row address row address real status command busy io0=0 sucessful program io0=1 error in program copy back data input command col add1 row add1 row add2 col add2 col add1 row add1 row add2 col add2 column address col add1 col add2 i/ox r/b r/b tr tprog i/o7~0 00h 35h col add 1,2 & row add 1,2 col add 1,2 & row add 1,2 col add 1,2 85h 85h 10h i/ox 70h address address address data out data in data in
rev 1.2 / dec. 2009 30 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 18 : block erase operation (erase one block) figure 19 : read id operation 90h cle ce we ale re i/o x 00h trea read id command address 1 cycle maker code device code adh 4th cycle 3rd cycle f1h 1dh 00h tar twc cle ce we ale re i/o x r/b twb tbers busy 70h i/o0 row add1 row add3 60h auto block erase setup command erase confirm command read status command i/o0=0 successful erase i/o0=1 error in erase block address d0h
rev 1.2 / dec. 2009 31 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 20 : reset operation timing ffh t rst we ale cle re io7:0 r/b
rev 1.2 / dec. 2009 32 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 21 : read operation with read cache 00h ale ce cle we re r/b i/ox trbsy trbsy trbsy trbsy 30h col. add1 col. add2 row. add1 row. add2 31h 31h 31h data cache page buffer cell array 31h a dout n dout m dout m dout n+ dout n dout n+ 3fh dout m dout n dout n+ dout m dout n dout n+ tr a ale ce cle we re r/b i/ox 1 1 1 4 5 6 7 8 9 2 3 2 3 3 page n page n page n page n + 1 4 5 5 page n + 1 page n + 1 page n + 2 6 7 7 page n + 2 page n + 2 page n + 3 8 9 page n + 3 page n + 3
rev 1.2 / dec. 2009 33 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 22 : power on and data protection timings 10 us 2.5 v (v th ) v cc we wp
rev 1.2 / dec. 2009 34 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 23 : ready/busy pin electrical specifications rp value guidence rp (min) = = where il is the sum of the input currnts of all devices tied to the r/b pin. rp(max) is determined by maximum permissible limit of tr @ vcc = 3.3 v, ta = 25c, c l =50pf fig. rp vs tr, tf & rp vs ibusy vcc (max.) - v ol (max.) 3.2v p$?, l i ol + ?, l rp ibusy rp (ohm) ibusy ibusy [a] tr, tf [s] tf 2.4 200 150 1.2 50 100 0.8 0.6 1.8 1.8 1.8 1.8 busy ready vcc v oh tr tf v ol v ol : 0.4v, v oh : 2.4v vcc 300n 3m 1k 2k 3k 4k 200n 2m 100n 1m gnd device open drain output r/b tr
rev 1.2 / dec. 2009 35 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affe ct the performance of valid blocks becaus e it is isolated from the bit line and common source line by a select transistor. the devices are su pplied with all the locations in side valid blocks erased(ffh). the bad block information is written prior to shipping. any block where the 1st byte in the spare area of the 1st or 2nd th page (if the 1st page is bad) does not contain ffh is a ba d block. the bad block information must be read before any erase is attempted as the bad block information may be eras ed. for the system to be able to recognize the bad blocks based on the original information it is recommended to crea te a bad block table following the flowchart shown in figure 24. the 1st block, which is placed on 00h bloc k address is guaranteed to be a valid block. figure 24 : bad block management flowchart note : - make sure that either the 1st or 2nd page of every init ial block has not ffh data at the column address of 2048. <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh
rev 1.2 / dec. 2009 36 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash bad block replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying th e rest of the replaced block to an available valid block. refer to table 18 and figure 25 for the recommended procedur e to follow if an error occurs during an operation . table 18 : block failure figure 25 : bad block replacement note : 1. an error occurs on the block a during program or erase operation. 2. data in block a is copied to same location in block b which is valid block. 3. n th data of block a which is in controll er buffer memory is copied into n th page of block b 4. bad block table should be updated to prevent from erasing or programming block a operation recommended procedure erase block replacement program block replacement read ecc (with 1bit/512byte) 'dwd %xiihuphpru\riwkhfrqwuroohu %orfn$ %orfn% qsdjh ))k 'dwd ))k )dloxuh wk qsdjh wk
rev 1.2 / dec. 2009 37 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash 80h 10h t ww we i/ox wp r/b ww t 80h 10h we i/ox wp r/b 60h t ww d0h we i/ox wp r/b 60h t d0h ww we i/ox wp r/b write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enaled and disaled as follows (figure 26~29) figure 26 : enale programming figure 27 : disale programming figure 28 : enale erasing figure 29 : disale erasing
rev 1.2 / dec. 2009 38 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash ' $ ',( $ h % / . ( ( & &3 $
rev 1.2 / dec. 2009 39 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash figure 31. 63-ball fbga - 9 x 11 ball array 0.8mm pitch, package outline table 20. 63-ball fbga - 9 x 11 ball array 0.8mm pitch, package mechanical data symbol millimeters min typ max a 0.800.901.00 a1 0.25 0.30 0.35 a2 0.55 0.60 0.65 b 0.400.450.50 d 8.909.009.10 d1 4.00 d2 7.20 e 10.90 11.00 11.10 e1 5.60 e2 8.80 e0.80 fd 2.50 fd1 0.90 fe 2.70 fe1 1.10 sd 0.40 se 0.40 ' ' 6' )' )' $ $ $ 6( )( )( ( ( %$//3$ ( h h ggg h e '
rev 1.2 / dec. 2009 40 1 H27U1G8F2B series 1 gbit (128 m x 8 bit) nand flash marking information - tsop1 / fbga marking example k o r h 2 7 u 1 g 8 f 2 b y w w x x - hynix - kor - H27U1G8F2Bxx-xx h: hynix 27: nand flash u: power supply 1g: density 8 : bit organization f: classification 2: mode b: version x: package type x: package material x: bad block x: operating temperature - y: year (ex: 8=year 2008, 9= year 2009) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u (2.7 v~3.6 v) : 1 gbit : 8(x8) : single level cell+single die+large block : 2(1nce & 1r/nb; sequential row read disable) : 3rd generation : t(48-tsop1), f(63-fbga) : blank(normal), r(lead & halogen free) : b(included bad block), s(1~5 bad block), p(all good block) : c(0 x x - x x

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